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Characterization of floating-gate memory device with thiolate-protected gold and gold-palladium nanoclusters

Year: 2018

Journal: AIP Adv., Volume 8, JUN

Authors: Yokoyama, Takaho; Hirata, Naoyuki; Tsunoyama, Hironori; Negishi, Yuichi; Nakajima, Atsushi

Organizations: JSPS KAKENHI [15H02002, 17H06226]

The floating-gate memory characteristics of thiolate-protected gold (Au:SR) and palladium doped Au (AuPd:SR) nanoclusters, Au-25(SR)(18), Au24Pd(SR)(18), and Au-38(SR)(24) (R = C12H25), were investigated by capacitance-voltage (C-V) measurements in vacuum. Monolayer films of Au:SR nanoclusters were formed as floating-gate memory layers on p-type Si substrates by the Langmuir-Schaefer method with surface pressure - area (pi-A) isotherm measurements. A fluoropolymer (CYTOP, similar to 15 nm thick) was spin-coated on top to form a hydrophobic insulating layer. Using an Au pad (similar to 40 nm thick) as the gate electrode, C-V measurements exhibit clockwise hysteresis curves originating from the Au:SR and AuPd:SR nanoclusters against the reference measured in each sample, and the hysteresis widths were dependent on the composition and sizes of the Au:SR nanoclusters. The positive and negative voltage shifts in the hysteresis can be explained in terms of electronic structures in Au:SR and AuPd:SR-based devices. (C) 2018 Author(s).